In logic circuits, timing of logic (digital) signals is very important. When a logic signal is applied to a logic circuit through a signal path, the delay time of the signal path must be stable in order for the logic circuit to operate properly. When a plurality of logic signals are transmitted, the delay times of the signal paths must be equal to each other for maintaining the timing relation of the logic signals. In logic measurement instruments such as logic analyzers, the correct timing relation of a plurality of logic signals cannot be measured, if the delay time of each signal path is different, i.e. if the skew time of each logic signal is different. However, the delay time of the signal path is not constant and stable, since it depends on the length of the path, the propagation delay times of logic devices (ICs) in the signal path, etc. In particular, the propagation delay times of logic devices are affected by production variations, and vary in accordance with temperature
Therefore, a variable delay circuit is necessary to adjust the delay time of the signal path. Many variable delay circuits have been proposed, and one of them is shown in FIG. 1. Four individual delay devices comprising buffer ICs 12 through 18 are connected in series, and the input of the buffer 12 is connected to the input terminal 10 of the delay circuit. Terminal pairs 20 through 28 are connected between the input/output of each buffer and the output terminal 30 of the delay circuit. Delay lines may be used for the delay devices instead of buffers 12 through 18. The delay time of this variable delay circuit is adjusted by selectively shorting one of terminal pairs 20 through 28. However, it is troublesome to change the delay time frequently, since the previously shorted terminal pair must be opened before shorting another terminal pair. Moreover, the delay time cannot be controlled remotely, and it is not easy to measure the delay time because the timing relation of logic signals at the input and output terminals 10 and 30 must be measured. Another conventional variable delay circuit employs mechanical switches instead of terminal pairs 20 through 28 of FIG. 1. However, the switches are cumbersome, an the disadvantages of FIG. 1 are not improved.